Engineers who faced coverage gaps firsthand.
After years on verification teams, we saw coverage gaps return at tapeout. BigEndian is the tool we wanted then.
The beginning
Sunil and Priya collaborated first on a complex SoC effort, extending verification for a design nearly three years in progress. Two weeks before tapeout, coverage holes remained in the AXI interconnect and DMA controller, untouched by every directed test. The whole team saw the gaps, but no quick path to close them existed.
The issue was structural rather than a resource shortage. Teams write testbenches early, before the design is well understood. Reaching corner-case stimulus for arcs exposed late in development demands the final RTL state. Once that state is known, tapeout pressure makes new test infrastructure the highest-risk option. Coverage therefore accumulates gaps where repair is most difficult.
BigEndian takes the opposite route: it generates tests from the design itself, reading RTL hierarchy and current coverage state to synthesize targeted constraints. No testbench rewrite or simulator migration, just closure on key arcs before tapeout. Founded in Hyderabad in 2024, BigEndian received angel backing in 2025. It works with a small group of early-access pilot teams on complex SoC and chiplet designs.
The BigEndian team
Sunil has built RTL simulation infrastructure for complex, large-scale SoC programs. His work includes diagnosing coverage gaps in hierarchical designs and supporting verification teams through the final weeks before tapeout sign-off.
Priya works across formal verification research and constraint-solver design. She has built assertion-synthesis tools for protocol-heavy interconnect RTL, spanning formal property checking and simulation-based validation, and leads BigEndian's core test-generation engine.
Arjun led verification closure on multi-die chiplet programs where coverage coordination across die boundaries created distinctive gap patterns. He focuses on connecting simulation and formal methods so teams can distinguish simulation-reachable arcs from formal-only ones.
Contact us
Hyderabad, Telangana 500081
India