Verification Team Notes
Field notes on pre-silicon coverage, test generation, and tapeout readiness.
How Coverage Gaps Outlast Review in Complex RTL
Every verification team has seen a report at 94 percent functional coverage and asked: where is the remaining 6 percent, and does it matter? The second answer is rarely simple.
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Beyond Directed Tests: Constrained Random for SoCs
Every verification team has seen a report at 94 percent functional coverage and asked: where is the remaining 6 percent, and does it matter? The second answer is rarely simple.
Closing the Last 10 Percent Before Tapeout with Agents
The final 10 percent can consume the last two weeks of a tapeout schedule. A team may see 91 or 92 percent in its coverage report while the remaining 8 to 9 percent of bins are distributed across dozens of modules.
AXI Handshake Assertions by Synthesis
When AWVALID and AWREADY meet on a rising edge, the address handshake is complete, but verifying every legal AXI4 handshake sequence is far less bounded than the basic rule suggests.
Why Coverage Closure Stalls at 90 Percent
The first 90 percent of functional coverage usually comes from standard regression infrastructure. With a UVM testbench, reasonable constraints, and a few thousand seeds over a few weeks, well-instrumented RTL blocks...
From Design Intent to Stimulus: Generating SystemVerilog Constraints
A completed design specification and an exercised testbench are not the same thing. The specification states intended behavior, while the testbench must create stimulus that tests whether the implementation meets it.
Formal Verification and AI Test Generation Work Together
In a real chip workflow, formal and simulation run alongside each other, not as rival bets. A team writes a property for a 32-deep FIFO, waits an hour, and gets either a timeout or a proof limited to an arbitrary k-step...
Chip Respin Economics: Why Coverage Closure Matters
A chip respin can run $5M to $20M, while redesign and re-sign-off can consume 8 to 12 weeks. No team plans to absorb that bill. It arrives after a late discovery as a cost that should have been avoided months earlier.
Adding a Second Die Changes Verification Scale
Chiplet architectures aimed to improve the economics of large die silicon. Splitting a monolithic SoC into smaller tiles lets teams pair compute and memory density with suitable process nodes, while limiting the yield...
What Coverage Completeness Means at Tapeout
What does coverage completeness actually mean at sign-off? Every verification plan names coverage criteria, but few define them precisely enough to guide a tapeout decision.
Reset Sequencing Races in RTL Testbenches
Reset sequencing races are a specific RTL bug class that hand-written directed testbenches routinely miss. Such benches find the cases their authors predicted.
Evaluating AI-Assisted Verification on a Chip Team
Adding verification tooling during an active chip project is a risk decision as much as an engineering decision.
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