The final 10 percent can consume the last two weeks of a tapeout schedule. A team may see 91 or 92 percent in its coverage report while the remaining 8 to 9 percent of bins are distributed across dozens of modules. At standard random run rates, those bins can require an unknowable amount of simulation. The immediate questions are which bins are reachable, which point to real bugs, and how to close the gap before time expires.
This is the last 10 percent problem, and it differs materially from the earlier verification stages. Random tests under reasonable constraints close the first 90 percent quickly by reaching common paths naturally. The final 10 percent is difficult because its paths remain outside random exploration unless the stimulus receives precise direction.
Why the Last 10 Percent Is Different
Consider the uncovered space at 90 percent. Major protocol paths have been exercised, normal operating modes have run, and common bins in the coverage model are green. The remaining work usually fits into three categories.
First are deeply nested error states that depend on a precise event sequence. Defining them is straightforward, but random stimulus rarely produces the required order. A million seeds might reach the bin only once.
Second are multi-cycle timing behaviors that depend on two signals holding a precise relationship for one or two cycles within a critical sequence. For example, an interrupt pending flag may set as a DMA transfer completes while a status register is cleared. Each event is common by itself, but their overlap is rare. Standard constrained random does not capture inter-cycle timing relationships between independent stimulus threads unless constraints are added. Discovering the required constraints first requires knowing that the timing window exists.
Third are interaction-dependent behaviors involving two or three subsystems in particular states at the same time. Subsystem A may show 97 percent coverage and subsystem B 95 percent, while the cross-coverage bin for "A in state X while B in state Y" remains at zero. Each subsystem reaches its target state under a different traffic pattern, so the patterns do not naturally occur together.
More regression cycles do not produce a proportional improvement for these bins. Coverage gained per simulation hour falls sharply. Directed tests for each open bin can work, but a verification engineer must reverse-engineer the required stimulus manually. For a complex SoC with 200 bins still open during the last two weeks before tapeout, that workload does not scale across the team.
How Agents Take a Different Path
At BigEndian, our method examines the structure of each uncovered arc instead of simply adding simulation cycles. We ask, "What stimulus sequence is structurally required to reach this arc?" rather than, "How many more seeds will close this bin?"
That analysis combines the coverage database with the RTL. The database identifies open bins and their coverpoints. The RTL exposes the predecessor states and input conditions needed to reach each arc. Together, they support a targeted stimulus template: the smallest sequence of transactions and state conditions that moves the design toward the uncovered arc.
The agent does not produce a finished test. It adds or relaxes constraints so the uncovered arc becomes much more likely during a standard UVM test run. A probability of 1-in-a-million can become 1-in-50. The process remains random, preserving useful timing variation, but the target arc appears within a practical number of runs.
In internal pilot data from three early-access teams, targeted arc analysis shortened closure time for the specific final 10 percent bins by roughly 60 percent versus extended random regression. That figure needs context because it covers particular designs and coverage models, whose details matter more than an aggregate result. The direction has remained consistent: targeted guidance reaches difficult bins sooner because random exploration cannot reach them efficiently.
Where the Agent Still Falls Short
An agent using coverage data and RTL structure cannot repair an incomplete coverage model. When a coverage group lacks a bin for a behavior, the agent has no signal that the behavior exists. A state machine transition behind a post-silicon bug may therefore be absent from the coverage database because no coverpoint was defined for it.
This limitation matters most. Automated coverage closure speeds work against gaps already represented in a defined model, but it does not check whether the model itself is complete. That assessment depends on the design specification, architecture intent, and known failure modes for the design class. Agents assist with verification execution. Engineers still own coverage planning and its judgment calls.
Designs containing substantial IP blocks without available RTL introduce another constraint. If arc analysis depends on the RTL of licensed IP and that source cannot be accessed, reachability analysis inside the block is limited. In practice, last 10 percent closure usually centers on custom RTL owned by the team, where full structural analysis is available.
Adding Targeted Analysis to the Regression Flow
Teams evaluating this method usually ask whether it requires changes to their UVM infrastructure. In most cases, it does not. Targeted arc analysis produces constraint changes and sometimes a test class around a specific stimulus sequence. Both fit into a standard UVM regression. The changes can be additional constraint blocks or weight overrides applied to existing sequence items without changing those items.
A practical flow is to use standard nightly regression through most of verification, then move to targeted arc analysis during the final two to three weeks. Nightly regression efficiently drives the first 88 to 92 percent of coverage, while targeted runs address the difficult bins. This preserves the existing methodology and optimizes the phase most exposed to schedule pressure.
The final tapeout push is not about reaching a perfect coverage number. It is about establishing that open bins are unreachable during normal operation or have explicit waivers with documented rationale. Faster closure changes the discussion from "we are still running tests" to "these are the specific arcs we waived, and this is why."