The first 90 percent of functional coverage usually comes from standard regression infrastructure. With a UVM testbench, reasonable constraints, and a few thousand seeds over a few weeks, well-instrumented RTL blocks commonly move from zero to roughly 88 to 92 percent. The final stretch behaves differently. Random exploration saturates around that range, leaving behaviors that require targeted analysis instead of more simulation.
The plateau is where the real decision starts. When additional random simulation stops improving coverage, the team must choose an approach that affects schedule, quality, and staffing. That choice depends on identifying why progress stopped, which calls for a different analysis method than the one used to reach 90 percent.
Coverage Plateau Structure
A plateau is rarely spread evenly. At 91 percent functional coverage, the remaining 9 percent is usually concentrated in a small set of bins, often across two or three covergroups. Most of the remaining coverage model is already closed.
That distribution reveals the kind of gap you have. If one or two bins remain open in each of 20 covergroups, the issue is breadth: constrained random reaches many behaviors only occasionally. If two or three covergroups contain most of the open bins, the issue is likely depth. Those behaviors need stimulus conditions that current constraints cannot produce often enough.
The remedy differs between breadth and depth. Breadth gaps often respond to relaxed constraints or targeted weight overrides on existing sequences. Depth gaps generally call for new stimulus infrastructure, such as a sequence class, constrained object, or, in some cases, a directed test that drives the required condition directly.
Three Common Causes
Coverage reports from the designs we examined during early access point to three structural patterns behind most plateaus above 90 percent.
The first pattern is hidden ordering in the stimulus. A UVM virtual sequence coordinates multiple agents, yet its ordering can unintentionally block the state cross-product needed by some bins. If agent A's transaction always finishes before agent B's transaction begins, a bin requiring both agents to be mid-transaction simultaneously can never hit. No constraint block states this directly. The behavior comes from the virtual sequence implementation, so the sequence logic must be inspected alongside the coverage report.
The second pattern is absent constraint modes for errors and boundary conditions. Most UVM testbenches use the happy path as their default constraint profile. Error injection and boundary cases may exist in separate test classes, but they often receive too little weight in the main regression. Error recovery and boundary-value covergroups therefore retain open bins because their tests run infrequently or their constraints cover too narrow a portion of the boundary space.
The third pattern involves cross-coverage bins that depend on simultaneous activity in independent subsystems. Consider a cross of "DMA transfer active," "interrupt pending," and "power domain transition active." Each condition may be common alone, but their overlap depends on the rate of each event. If the expected overlap is once per ten thousand transactions, a regression with fifty seed runs averaging two thousand transactions each is unlikely to close that bin.
Bin-Level Analysis
Start plateau analysis with the open bins, not the closed ones. Extract every bin with zero hits across the full regression history and sort the results by covergroup. Then trace each bin's condition through the stimulus chain: which transactions must be active, what DUT state is required, and what timing relationship must occur?
This tracing is manual, but the workload is usually manageable. In a mature coverage database, zero-hit bins form a bounded list. Internal pilot data from three early-access teams showed counts ranging from roughly 40 to 120 bins at 90 to 93 percent coverage across their SoC blocks, depending on model complexity. Tracing reachability for each bin takes five to fifteen minutes, a defined task compared with running more seeds and hoping.
After reachability conditions are recorded, the bins usually sort into natural groups. Bins sharing conditions may close through one constraint change. Bins needing new stimulus sequences can be implemented together. Bins that prove unreachable, such as dead code paths or protocol states unavailable during normal operation, can be documented for waiver.
Waivers
An open bin does not always indicate a missing test. The coverage model may have been created before RTL completion, while planned states were later removed or combined. Such bins should receive a waiver explaining why the condition cannot occur, rather than a directed test for a path that production silicon will never take.
Every waiver needs a documented rationale tied to RTL. Identify the exact conditions that prevent reachability: for example, leaving state S requires input condition C, while upstream logic always blocks input condition C. A waiver without that RTL-based explanation weakens tape-out sign-off credibility. In our experience, it is also the first item a chip architect questions during final coverage review.
Coverage waivers are not inherently poor practice. A verification plan with zero waivers at tape-out may be overconstraining simulation, running an impractically long campaign, or using an overly conservative coverage model. Some waivers are valid. The requirement is to document each one clearly enough for others to review the decision.
Work Priorities
Suppose 80 bins remain open at 91 percent coverage and all must be closed or waived before tape-out. Prioritization is essential. Error handling and recovery state machines deserve higher attention because post-silicon bugs often appear there during bring-up. Power management cross-coverage is also high-risk in complex SoC designs. Arithmetic and address-calculation boundaries are medium-risk. Utility state machines with limited behavioral impact rank lower.
More random simulation is not prioritization. Moving from 91 percent to 97 percent requires identifying the specific 6 percent that remains and deciding what to do with every bin. It does not depend on waiting for the constraint solver to happen upon the right sequence. Teams that finish efficiently switch from simulation volume to bin-level analysis when the plateau appears, before schedule pressure becomes acute.