Platform

Tests derived from RTL, not templates.

BigEndian maps design hierarchy to testbench blind spots, then synthesizes coverage-driven tests for uncovered arcs and state spaces.

Test Generation

How BigEndian maps and targets your design

The agent loads your RTL hierarchy with an existing coverage database. It parses the module tree, finds unreached branches, unexercised FSM arcs, and uncovered condition combinations, then synthesizes SystemVerilog constraint blocks and assertion templates for those gaps.

Generated tests are reviewable SystemVerilog files your team can commit with its testbench code. No black-box output.

Module Line Branch FSM
axi_master
94%
88%
71%
axi_slave
91%
63%
38%
dma_ctrl
87%
74%
42%
int_ctrl
96%
92%
85%
cache_ctrl
68%
31%
22%
Coverage Loop Architecture

Every iteration focuses on open arcs

The agent does not rerun random generation. After each simulation, it reads the new coverage report, finds the arcs still open, and synthesizes constraints aimed at those exact gaps.

RTL + Coverage DB
Gap Analysis
SV Constraint Synthesis
Simulation Run

Continue until coverage targets are met or the team marks remaining simulation gaps as unreachable and suited to formal verification.

Simulator Integration

Connect with your sim environment

BigEndian uses a small config file. Set the top-level module, Makefile, and coverage database. No simulator migration or testbench rewrite is required.

Supported simulators

  • Synopsys VCS
  • Cadence Xcelium
  • Mentor Questa
  • Riviera-PRO (coming soon)

Coverage metric support

  • Line coverage
  • Branch coverage
  • Condition coverage
  • FSM state and arc coverage
  • Toggle coverage

Example config (bge.yaml)

rtl:
  top: soc_top
  files: ./rtl/**/*.sv
  include_dirs: [./rtl/include]

simulator:
  tool: vcs
  makefile: ./Makefile
  coverage_db: ./sim/coverage.db

targets:
  line: 95
  branch: 90
  fsm: 85

output:
  dir: ./generated_tests
  format: systemverilog
System Requirements

What you need to begin

Language support

SystemVerilog (full support), VHDL (partial support, mixed-language designs accepted).

Design size

Best suited to designs of 10,000 lines or more, where reachable coverage and achieved coverage often diverge most.

Deployment model

Cloud-based AI engine: no local GPU install required. Use the REST API or lightweight CLI wrapper before your existing sim Makefile.

RTL confidentiality

RTL runs in an isolated compute environment and is not retained after the session. Enterprise plans support private cloud and on-premises deployment.

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